help on SDRAM

Hi sol,

While not SDRAM-specific, there is a document in Nios II 5.0 which may help you understand how to calculate phase-shift values and determine how fast you can run SDRAM without using a PLL for phase-shifting. The document describes the new SSRAM interface in Nios II 5.0 and is "ssram_interface_readme.html" in the Nios II installation's 'documents' folder.

You should study carefully the first section that describes the memory interface with no phase shift -- it will show you how to calculate the maximum speed which you can run with no phase shift. You will need:

1. To obtain the data sheet for your SDRAM and examine timing parameters (Tsu, Tco for all inputs, worst-case)

2. Look at the quartus timing analysis report for Tco and Tsu times for all pins to and from SDRAM

3. Perform timing analysis to see what f-max you can run at with no phase shift

Important note: Even without a PLL there will be a phase-relationship between FPGA (Avalon) clock and the clock you drive from the FPGA to SDRAM. You should be able to find this delay in the Quartus Tco report.

Good luck!