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Altera_Forum's avatar
Altera_Forum
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14 years ago

help: niosII and pof/sof

Hello,

Hopefully this has a simple solution. I have a board with an Arria GX which can be programmed with through an active serial EPCS64 using a pof file.

I've created a very simple system with Qsys containing -

niosII/f - data cache disabled (went with f because I have a 120MHz clock connected)

-- level 1 jtag debug interface

sysid block

interval timer (full features)

jtag uart

RAM (will explain why later)

----------

The system compiles nicely and I can successfully program this to my chip as a pof file.

Note that I wasn't 100% sure what contraints to use, so i used the settings from hw_dev_tutorial.sdc updating only the system clock speed to match the 120MHz oscillator connected to my board.

I've created a bsp and nios application using the Nios Eclipse SBT hello world template.

i changed the bsp properties to

+ reduced device drivers (cased on examples)

- support c++ (I only will be coding in C for this app)

- grof support (not profiling right now)

+ small C library

The BSP builds fine.

The Application builds fine.

However, when I try to Run As Nios II Hardware, the run configurations gives me the following message:

"[Target Connections]: No Nios II target connection paths were located. Check connections and that a Nios II .sof is downloaded."

???

My Quartus compiled generated both an sof and a pof, but I used the pof to program the device.

Do I need to be able to program my device with an sof? I seem to be having a problem with this in QII... It works great on my Cyclone III dev board, but ..

Thanks!

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Daixiwen,

    I seem to have the same problem with the SBT Flash programmer - it requires that a jtag debug core be present in the device design. (Table 1-1 of the Nios II Flash Programmer User Guide.)

    Recall that my jtag signals are not connected: (TDO,TRST both NC, TDI,TMS both Vcc, TCK GND)

    --- Quote End ---

    Yes I know, that's why I suggested to use the Quartus programmer instead. I've never used this method, but I know there is a way to convert an .elf file into a flash file that the Quartus programmer can understand, and place in the EPCS just after the FPGA image.
  • Altera_Forum's avatar
    Altera_Forum
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    When you download .sof file, you must make the button of DE2 borad on RUN, and when you download .pof file ,you have to make the button of DE2 borad on PROG, so I think you may not make the button on PROG,it is sure be failed.