--- Quote Start ---
Daixiwen,
I seem to have the same problem with the SBT Flash programmer - it requires that a jtag debug core be present in the device design. (Table 1-1 of the Nios II Flash Programmer User Guide.)
Recall that my jtag signals are not connected: (TDO,TRST both NC, TDI,TMS both Vcc, TCK GND)
--- Quote End ---
Yes I know, that's why I suggested to use the Quartus programmer instead. I've never used this method, but I know there is a way to convert an .elf file into a flash file that the Quartus programmer can understand, and place in the EPCS just after the FPGA image.
Honored Contributor
