Honored Contributori am a beginner of this field. so many problems block me.
i have a ep1s80 dev board and a ep1s25 dev board.but i can't program flash on these board. the preset of the cfi does't support these type flash(amd29lv640 and amd29lv320dt).and the timing value also puzzled me.does someone show me how modify the timing value? thank you ver much.
Honored ContributorHello ffone13,
In the topic http://www.niosforum.com/forum/index.php?a...t=st&f=17&t=455 (http://www.niosforum.com/forum/index.php?act=st&f=17&t=455) there were discussed some problems with the flash programmer. Perhaps it is helpful for you. Are you using development boards from Altera? Which Nios version are you using? Bye, niosIIuserHonored Contributorhello niosIIuser
yes,i am using development board from altera.my nios is :niosii ;niosii ide Version: 1.0.0;quartus 4.0+sp1. i used "flash_tests" from niosii ide to test the flash ,the console said: can't open flash device.and if used "hello_world",it's ok. i only run program not "flash program". i think my problem is how to modify cfi to accomodate my flash.Honored ContributorThis means that the call to alt_flash_open_dev(EXT_FLASH_NAME) is failing.
This could be failing for a number of reasons: If you have Use reduced device drivers selected for your system library then the CFI component is excluded. See section 4-23 of the Nios II Software Developers Handbook If this is not the case I suggest you stick a break point in the function alt_flash_cfi_init in the altera_avalon_cfi_flash component under you Nios II Device Drivers project and find out why this function is failing.Honored Contributorthank you for reply.
the posibility is excluded.i did not select the reduced device drivers option. the second reason i have not proved. tomorrow i'll have a try. my flash support cfi ,but i can't determine the timing value. another question:when i select APEX20KE from Target Device Family,the status showe error information : cpu requires Stratix ,StratixII ,Cylone device to operate. Please change the target device selection. Does the quartusII&niosII support APEX family device?Honored Contributorcpu requires stratix ,stratixii ,cylone device to operate. please change the target device selection.
does the quartusii&niosii support apex family device? --- Quote End --- The Apex family is not supported by Nios II!
Honored Contributorhello rugbybloke
i follow your suggestion:stick a break point in the function alt_flash_cfi_init in the altera_avalon_cfi_flash component. when step into alt_read_cfi_width(alt_flash_cfi_dev* flash) in the altera_avalon_cfi_flash_table .c when execute : for(i=0;i<3;i++) { byte_id[i] = IORD_8DIRECT(flash->dev.base_addr, 0x10+i); } the result of the byte_id[0] =. byte_id[1] =. byte_id[3] =. and ret_code = -ENODEV; the ret_code is " -19" fd = alt_flash_open_dev(EXT_FLASH_NAME); the fd =0 i don't know what is the reason. my board is :Stratix dsp s80 dev. board rev. 1.2 the flash is: am29dl640d the only reason i think i don't config the flash right. help me!Honored Contributorffone13,
You're going to have to delve a little further. The code you're stepping through is trying to calculate the width of the flash connected to the processor. You will have to find exactly which line the -ENODEV is asserted on to determine what your problem is. PaulHonored Contributorhello rugbybloke,
firstly,i set a break point at alt_flash_cfi_init( alt_flash_cfi_dev* flash ) in altera_avalon_cfi_flash .c then execute : alt_read_cfi_width( flash ); i step into the function. then execut : alt_write_flash_command_8bit(flash->dev.base_addr, 0x55, QUERY_MODE); i can't trace at this sentence : IOWR_8DIRECT(base_addr, offset, value); int alt_read_cfi_width(alt_flash_cfi_dev* flash) { int i; alt_u8 byte_id[12]; alt_u8 byte_iface; alt_u16 half_word_iface; alt_u32 full_word_iface; int ret_code = 0; alt_write_flash_command_8bit(flash->dev.base_addr, 0x55, QUERY_MODE); for(i=0;i<3;i++) { byte_id = iord_8direct(flash->dev.base_addr, 0x10+i);}
if ((byte_id[0] == 'q') &&
(byte_id[1] == 'r') &&
(byte_id[2] == 'y'))
{
flash->native_word_size = 1;
byte_iface = iord_8direct(flash->dev.base_addr, 0x28);
byte_iface += 1;
if (!(byte_iface & 0x1))
{
ret_code = -enodev;
}
}
else
{
/*
* put the device back into read array mode
*
* not strictly necessary i think
*/
alt_write_flash_command_8bit(flash->dev.base_addr, 0x55, read_array_mode);
/*
* try to put the device into query mode
*/
alt_write_flash_command_16bit(flash->dev.base_addr, 0x55, query_mode);
for(i=0;i<6;i++)
{
byte_id = IORD_8DIRECT(flash->dev.base_addr, 0x20+i); } if ((byte_id[0] == 'Q') && (byte_id[1] == '\0') && (byte_id[2] == 'R') && (byte_id[3] == '\0') && (byte_id[4] == 'Y') && (byte_id[5] == '\0')) { flash->native_word_size = 2; half_word_iface = IORD_16DIRECT(flash->dev.base_addr, 0x28*2); half_word_iface += 1; if (!(half_word_iface & 0x2)) { ret_code = -ENODEV; } } else if ((byte_id[0] == 'Q') && (byte_id[1] == 'Q') && (byte_id[2] == 'R') && (byte_id[3] == 'R') && (byte_id[4] == 'Y') && (byte_id[5] == 'Y')) { flash->native_word_size = 2; half_word_iface = IORD_16DIRECT(flash->dev.base_addr, 0x28*2); half_word_iface += 1; if (!(half_word_iface & 0x2)) { ret_code = -ENODEV; } } else { /* * Put the device back into Read Array Mode */ alt_write_flash_command_16bit(flash->dev.base_addr, 0x55, READ_ARRAY_MODE); /* * Try to put the device into Query mode */ alt_write_flash_command_32bit(flash->dev.base_addr, 0x55, QUERY_MODE); for(i=0;i<12;i++) { byte_id[i] = IORD_8DIRECT(flash->dev.base_addr, 0x40+i); } if ((byte_id[0] == 'Q') && (byte_id[1] == '\0') && (byte_id[2] == '\0') && (byte_id[3] == '\0') && (byte_id[4] == 'R') && (byte_id[5] == '\0') && (byte_id[6] == '\0') && (byte_id[7] == '\0') && (byte_id[8] == 'Y') && (byte_id[9] == '\0') && (byte_id[10] == '\0') && (byte_id[11] == '\0')) { flash->native_word_size = 4; full_word_iface = IORD_32DIRECT(flash->dev.base_addr, 0x28*4); full_word_iface += 1; if (!(full_word_iface & 0x4)) { ret_code = -ENODEV; } } else if ((byte_id[0] == 'Q') && (byte_id[1] == '\0') && (byte_id[2] == 'Q') && (byte_id[3] == '\0') && (byte_id[4] == 'R') && (byte_id[5] == '\0') && (byte_id[6] == 'R') && (byte_id[7] == '\0') && (byte_id[8] == 'Y') && (byte_id[9] == '\0') && (byte_id[10] == 'Y') && (byte_id[11] == '\0')) { flash->native_word_size = 2; full_word_iface = IORD_32DIRECT(flash->dev.base_addr, 0x28*4); full_word_iface += 1; if (!(full_word_iface & 0x4)) { ret_code = -ENODEV; } } else if ((byte_id[0] == 'Q') && (byte_id[1] == 'Q') && (byte_id[2] == 'Q') && (byte_id[3] == 'Q') && (byte_id[4] == 'R') && (byte_id[5] == 'R') && (byte_id[6] == 'R') && (byte_id[7] == 'R') && (byte_id[8] == 'Y') && (byte_id[9] == 'Y') && (byte_id[10] == 'Y') && (byte_id[11] == 'Y')) { flash->native_word_size = 1; full_word_iface = IORD_32DIRECT(flash->dev.base_addr, 0x28*4); full_word_iface += 1; if (!(full_word_iface & 0x4)) { ret_code = -ENODEV; } } else { ret_code = -enodev;// the ret_code get -19 at this place } /* * Put the device back into Read Array Mode */ alt_write_flash_command_32bit(flash->dev.base_addr, 0x55, READ_ARRAY_MODE); } } return ret_code; }
Honored Contributorit seems that the byte_id get nothing when excute :byte_id = IORD_8DIRECT(flash->dev.base_addr, 0x10+i); in despite of write flash is 8 bit or 16 bit command mode.
can the Nios II 1.0.1 solve the problem? the nios didn't recognise my flash.Honored Contributorffone,
The nios 1.01 release does contain a change in this function which was made to make it work with 16 bit flashes in 8 bit mode. The error you're getting is basically that the code cannot get a valid CFI response from the flash. I would recommend you try 1.01 .
