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Altera_Forum
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15 years ago

Help-about peripheral IP design

Hi,dear friends.

Recently I have done a DAC IP as a Nios peripheral but it doesn't meet the requirment.I do this IP as the example "pwm" from Altera.com.Now I send a series number to the dac(AD5547 parallel) output during the Nios IDE,the numbers are signals of 40KHz sampled by 1MHz.The output displayed in the oscilloscope is 23.0147KHz,watching the register during debugging ,all numbers have gone into the register.So I'm confused and then I reminded the cpu as fast,the result became 37.3130KHz.It's hard to understand what happened.

So I think maybe there are some problem between the transmition.So I consider some methods as list:

1、 SPI,but it is series peripheral interface,AD5547 is parallel,so it may doesn't fit.

2、 DMA

3 、FIFO

But I really don't know how to send the numbers to the DAC output.Maybe what I have done is totally wrong.

Could you give me some suggestions of how to design DA or AD peripherals?:)

Thanks a lot!

ps:

while(1)

{

for(i=0;i<=24;i++)

IOWR_ALTERA_AVALON_PIO_DATA(DATAOUT_BASE,sin_vector1[i]);

}

and I set the DAC control pios as the timegraph so DAC works normally.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The compiler can sometimes transform a simple for(;;) statement into one where the loop body occurs twice. One copy being executed for the first iteration and the other for all further ones.

    (I can't think of an example of when ....)

    This would mean that there are a different number of clocks between the first two writes than between all subsequent pairs.

    Since you are trying to generate a fixed frequency, so need an known (and user-defined) number of clocks between the outputs. This will probably require that you instert some extra 'nop' instructions as pads (look up 'asm volatile').

    There is very little info on the branch predictor, but basically the instruction prefetch and decode unit has to make an assumption as to whether a conditional branch will be taken or not.

    Static prediction assumes that backwards branch is assumed taken (ie assumed to be the botton of a loop), and that a forwards branch is assumed not-taken.

    The dynamic branch prediction logic uses the low bits of the program counter and the history of recent branches to index a table (default 256 entries) to determine what to do. This means that the first few iterations of a loop might be incorrectly predicted - leading to 2 additional clocks.

    (If a forwards branch is mis-predicted the cost is 3 clocks.)

    The dynamic branch prediction logic is standard in the /f processor. Altera no not publicise how to disable it.