Help-about peripheral IP design

The compiler can sometimes transform a simple for(;;) statement into one where the loop body occurs twice. One copy being executed for the first iteration and the other for all further ones.

(I can't think of an example of when ....)

This would mean that there are a different number of clocks between the first two writes than between all subsequent pairs.

Since you are trying to generate a fixed frequency, so need an known (and user-defined) number of clocks between the outputs. This will probably require that you instert some extra 'nop' instructions as pads (look up 'asm volatile').

There is very little info on the branch predictor, but basically the instruction prefetch and decode unit has to make an assumption as to whether a conditional branch will be taken or not.

Static prediction assumes that backwards branch is assumed taken (ie assumed to be the botton of a loop), and that a forwards branch is assumed not-taken.

The dynamic branch prediction logic uses the low bits of the program counter and the history of recent branches to index a table (default 256 entries) to determine what to do. This means that the first few iterations of a loop might be incorrectly predicted - leading to 2 additional clocks.

(If a forwards branch is mis-predicted the cost is 3 clocks.)

The dynamic branch prediction logic is standard in the /f processor. Altera no not publicise how to disable it.