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Altera_Forum
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16 years ago

Help-about peripheral IP design

Hi,dear friends. Recently I have done a DAC IP as a Nios peripheral but it doesn't meet the requirment.I do this IP as the example "pwm" from Altera.com.Now I send a series number to the dac(A...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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To remove jitter you'll need to ensure that the instructions take the same time each time thay are exectuted.

The dynamic branch prediction will scupper this.

As will any contention on the Avalon MM slave device.

(Even assuming there are no cacahe delays.)

You also need to check the assembler generated by the compiler to ensure the first loop iteration isn't coded separately.

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Thanks a lot!

I can not understant totally.I don't know about the dynamic branch prediction.

And you said checking the assembler generated by the complier to ensure the first loop iteration isn't coded separately. During my design there only have one peripheral,I don't understand the first loop iteration's meaning.

Best regards!