Help-about peripheral IP design

I see.Thank you for your kindness.

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some customer ips can have master and slave ports. a master like the nios cpu tells the customer ip via its slave ports that the next couple of data is stored under slave memory location 0xsomething and enables this ip functionality to fetch via its master ports the data without the help of some other master funtionality.

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Now if I want to design a AD IP,then it must have input ports and output ports.I'm not sure that whether the input data go into the fifo,and then fifo send the data to avalon bus,at last avalon bus write the data to AD IP register.It seems complex.

Besides,I occure another problem.I made a memory initialization(use Tightly-Coupled Memory).I want to get data from the on-chip-memory to dataout ports.But it doesn't work.(in the attachment)

during Nios IDE,I do like this

volatile int i;

volatile int *data_tcm_memory_ptr;

data_tcm_memory_ptr = (alt_u32*) (0x00000000);//on-chip-memory base

while(1)

{

for(i=0;i<=24;i++)

IOWR_ALTERA_AVALON_PIO_DATA(DATAOUT_BASE,(alt_u32*)(data_tcm_memory_ptr+i));

}

Best regards!