Help-about peripheral IP design

well, without more knowledge how your design is done between nios cpu and your dac i can't give you precise hints.

the avalon bus is similar to lets compare it with a telephone switching center, where masters (like nios cpu or DMA) cann call slaves (like memory or ip registers).

some customer ips can have master and slave ports. a master like the nios cpu tells the customer ip via its slave ports that the next couple of data is stored under slave memory location 0xsomething and enables this ip functionality to fetch via its master ports the data without the help of some other master funtionality.

such read and writes can be as fast a 1 clock cycle, but could also be longer depending upon waitstates a slave can assert if this slave is slower, or if the slaves is occupied by another master, in last case the calling master must wait until the currently accessing master is finished.