Honored Contributor
Honored Contributorconnect pins a1,a2,a3 to module pins a2,a3,a4.
tie pins a8,a9 high, all remaining address pins low.
irq and reset connected to obvious pins.# ior,# iow to# rd,#wr.# ads, aen low, lclk,# be2,#be3 high.
with the address lines connected as described, your registers should be on 32bit boundaries: base+0,base+4,base+8,etc.
as a test try to read the bsr:
write 0x0003 to base+0xe, then you should read something like 0x339n from base+0xa. you may have to use 0x1c,0x14 instead of 0xe,0xa depending on if you have used any of the built-in macros to do the job. once this works, you will know what kind of changes will be needed to the driver - mainly shift and mask.
the reason for using native addressing is to prevent the nios from doing two reads when you really want just one (data fifo access) . use a scope to see if you need to worry - it may not happen under 5.0. --- Quote End --- Sweet, I got it working. Nate Knight's 16-bit-friendly driver helped out too, although I had to fix the offsets for the IORD_8DIRECT calls and use regular IORD/WR for the rest. The IORD/WR calls work off Base+0, Base+2, Base+4 etc too which was nice. For the IORD_8DIRECT I had to use Base + (x * 4) for the low byte and Base + (x * 4 + 1) for the high byte. Next step is to stack two of these puppies and get three interfaces running simultaneously on the board. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif Thanks!
