Honored Contributor
Honored ContributorI have the altera daughtercard documentation, thanks though.
How did the change to native addressing help? I found an explanation of the difference but I'm still confused about what situations you'd use each in. Also how did you hook up your address and byte enable lines? Right now I have my daughtercard component hooked up to a separate tri-state bridge. It gives me address lines 3..0 and byte enable 1..0. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10794)</div> --- Quote End --- Connect pins# BE0,# BE1 to the same named module port pins. Connect pins A1,A2,A3 to module pins A2,A3,A4. Tie pins A8,A9 high, all remaining address pins low. IRQ and Reset connected to obvious pins.# IOR,# IOW to# RD,#WR.# ADS, AEN low, LCLK,# BE2,#BE3 high. With the address lines connected as described, your registers should be on 32bit boundaries: BASE+0,BASE+4,BASE+8,etc. As a test try to read the BSR: write 0x0003 to BASE+0xE, then you should read something like 0x339n from BASE+0xA. You may have to use 0x1C,0x14 instead of 0xE,0xA depending on if you have used any of the built-in macros to do the job. Once this works, you will know what kind of changes will be needed to the driver - mainly shift and mask. The reason for using native addressing is to prevent the nios from doing two reads when you really want just one (data FIFO access) . Use a scope to see if you need to worry - it may not happen under 5.0.
