Hard lock with Nios 2 cyclone dev board

Thanks for the response Soin, and you are correct, here is what I tried which is exactly what Altera provides the getting started guide:

1) open Quartus II 4.2 to the standard example.

2) select Tools -> programmer

3) check "program/configure" and click start

4) Quartus II reports the chip was successfully programmed (board is hard locked now)

5) start the Nios II IDE through SOPC builder

6) go to "New > C/C++ Applicaiton"

7) Select the Hellow World project and click finish

8) right click on the project and click "build project"

9) Nios II reports "Build Complete" so i select "Run..." from the Run menu

10) In there I click the "New" button for Nios II hardware

11) I select the USB-Blaster as my JTAG and the EP1C20 as the device

12) I click "Apply" and the "run"

13) I then get the error: "there are no Nios II CPU's with debug modules available which mach the values specified. Please check that your PLD is correctly configured, downloading an new SOF if necessary." And it pops the Quartus II programmer back up.

Now, I'm assuming that the board shouldn't be locked up between flashing the standard CPU and downloading the program code and that is the source of this error. Since I have never used an Altera board I can't say that for certain, but I'm assuming that is my problem. Any other ideas? should i try programming the EPCS with my FPGA configuration data? Thanks

-Jon