Gigabit Open Core is working properly

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originally posted by ilyak@Aug 16 2006, 01:48 AM

tri-mode ethernet mac is working now with simple interface to avalon and lwip

standalone tcp/ip stack(hal).

the system consists of cyclone ii and marvell phy 10/100/1000.

checked 100 and 1000 mbit/sec modes.

ilyak@avt-inc.com

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Hi,

I can&#39;t believe it, or maybe you don&#39;t mean the same core:

http://www.opencores.org/projects.cgi/web/...i_mode/overview (http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/overview)

In my point of view this core has some syntax errors (with Quartus II) e.g.:

-----xxxx snip xxxx------- file MAC-tx.v

//MAC_rx_flow ,

input [15:0] pause_quanta ,

input pause_quanta_val ,

);

//******************************************************************************

//internal signals

//******************************************************************************

Q2V6.0 SP1 reports:

Error (10170): Verilog HDL syntax error at MAC_tx.v(90)

near text ")"; expecting an identifier, or "input", or "output", or "inout", or "(*"

-----xxxx snip xxxx------- file MAC-tx.v

and finaly the CycloneII family doesn&#39;t cover the cores requirements:

Q2V6.0 reports:

-----xxxx snip xxxx-------

Error: M4K memory block WYSIWYG primitive "MAC_rx:U_MAC_rx|MAC_rx_FF:U_MAC_rx_FF|duram:U_duram|altsyncram:U_altsyncram

|altsyncram_0t22:auto_generated|ram_block1a0" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.

-----xxxx snip xxxx-------

Please report.

Kind regards Frank