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Altera_Forum
Honored Contributor
19 years ago --- Quote Start --- originally posted by grante@Oct 29 2006, 08:01 PM firstly, thanks for the help.
when connected to my real target board:
# ./jtagconfig
1) usb-blaster
020b30dd !
020a10dd !
captured dr after reset = (020b30dd020a10dd)
captured ir after reset = (55555) i expect two nodes, since that board has both the nios2 debug unit and the jtag uart.
when i run the gdb-server connected to my ral target, i get the same result as with the cyclone-ii.
yup, that's all i want is a working gdb-server. i can handle it from there.
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=19001)</div> --- Quote End --- The output from your jtagconfig command doesn't look correct. Is it possible that any of the IP you have built into your FPGA image is time limited? For instance, the Nios II processor can be run in "tethered" mode without a license, but a license is required for any other use of the core. On the Cyclone II Dev. Kit, are you sure you're using one of the included HW examples designs? They should have SOFs based on non-time-limited cores. Best Regards, - slacker