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Altera_Forum
Honored Contributor
Honored ContributorGate level simulation Custom Instruction
Hello, I have this problem: I have developed a multicycle custom instruction in vhdl. I have done an RTL simulation in modelsim and all works fine (I simulate the custom instruction only, wi...
Altera_ForumHonored Contributor
Honored ContributorI'm sorry but I can't post the code at the moment...what do you mean for good design practice? Separation of the sequential and combinatorial process, etc...I have suspected that the problem could be this, but why It works once loaded the system on fpga?
