frequency the Nios II processor can support is roughtly from 20 to 120MHz

The maximum freqency will depend on other parts of the sopc system, and how full (or rather empty) the fpga is.

The maximum will also require correct timing definitions during synthesis - since internal registers probably need to be replicated (etc).

I don't believe anything in the fpga is 'dynamic' (ie needs clocks to hold its state), so the minimum speed ought to be 0Hz - however the JTAG (and any other external interface) may enforce a minumim clock speed.

Also, any external memory (SRAM) is usually run with a clock generated by PLL to be a few ns ahead of the nios clock - this won't work if you are dynamically changing the clock speed.