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yeah i assume if we took the SOPC timing with consideration of the actual programs executing the software implemented pwm, the results will be even slower since the instructions won't be executed in parallel like the case of the programmed logic ...
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Right. The key is to understand is what you are analyzing. If you really wanted to analyze the timing of the PWM signals, you could run a Modelsim simulation and observe the PWM waveforms (generated by your toggling I/O software, or by a hardware PWM controller).
If your PWM waveforms were pulses to a stepper motor, and that motor expects slow pulses (Hz to kHz) and does not care about sloppy timing, then a software solution would work just fine.
If however, your PWM waveforms were to a digitally controlled power supply, where the PWM duty cycle affects the output voltage and current, then you would not want that control loop implemented in software alone.
Once you understand your system design requirements, and you understand the strengths and weakness of your CPU and/or FPGA, you can partition the design to the strengths of each. (FPGAs of course have no weaknesses ...)
Cheers,
Dave
Honored Contributor
