FPGAs and CPUs ??

How was your software model implemented? I assume you were toggling I/O pins.

When you toggle I/O pins from a CPU, you are subject to whatever else is going on on the processor, eg. RTOS interrupts, or on the bus, eg. DMA going on in parallel with your attempts to access the I/O registers. There is no way you can guarantee consistent timing when toggling an I/O.

An alternative implementation would be to create a PWM controller peripheral. This is how most microcontrollers work. In your case, you would implement the PWM controller to have just the features you wanted. Your software would program control registers and then enable the PWM controller. From that point on, the PWM waveform timing would be exactly as you coded the hardware.

Note that a TimeQuest timing analysis is only as good as the SDC constraints you provide, and it only tells you about timing relative to clocks, not relative to your software. I doubt you could infer anything useful between the timequest timing of an I/O pin relative to a PWM controller output pin. Both pins can be made to meet timing constraints (clock-to-output), but that will tell you nothing about the jitter (in units of whole clocks) in your software-generated PWM output.

Cheers,

Dave