ok here's the thing as a project i had to make pwm which consisted of 4 inputs to select the time base 4 inputs to select the duty cycle a clk input and one output connected to a led . i made a model using hardware implementation via QuartusII and VHDL and a model using software implementation in the Cyclone II processor on the FPGA board using SOPC Builder , Nios II and C code.
After performing the timing analysis for the SOPC model and the Hardware model the results were very in favor of the hardware model ... So i'm trying to understand why ? and if an FPGA was better than a cpu in this specific case in what case it could be the other way around?