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Altera_Forum
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20 years ago

FPGA startup - all I/O go to 1 for 0.5 seconds...?

Hi all, I am using NIOS-II Cyclone 2C35 evalution kit from Altera for project development. The problem is that after every power-up of the system the FPGA during reconfiguration sets all the I/O...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

yes, it is correct for most FPGA. the io pins will have weak pull-high before config done.

You can add pull low resistor on the pin where you want it stay low.