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Altera_Forum's avatar
Altera_Forum
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10 years ago

FPGA-SoC on Arrow SoCKit (Fitter error)

Hello Friends,

I am trying to learn Embedded System's on on Arrow SoC Board. http://rocketboards.org/foswiki/view/documentation/arrowsockitevaluationboard

1. I following the youtube Artical for my SoC Board. i have modified things according to my board like, Device, 8 Switch and 8 LED's etc.

www.youtube.com/watch?v=2wuket4-q7q (http://www.youtube.com/watch?v=2wuket4-q7q)

2. in this youtube video project--> its just a Blinking the LED through External switch. i have add only one hps and 8 led and 8 switch .

3. in my modified SoC Kit Project--> Analysis and synthesis is OK no issue. but during Fitter (Place and Route) it had lot's of error related to HPS connection. even though i have run tcl script.

I got following errors (attached) during fitter process.

Attached: (1) Project,

(2) Error Screen short,

(3) Qsys project screen short

How do i overcome this fitter problem....?

Regards

kaushalA

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You should download the GHRD and check the IO-Standards of the related PINs and also have a look to the *.tcl File for correct exclusion of fitter effort for that PINs, because they are fixed...

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    hello There

    OK i have download the ghrd design from rocketboard.org -->compile and follow the instruction-->port to board--> its working, i mean LED Glowing in a pattern etc.

    (1) Then as u mentioned in your post "check the IO-Standards of the related PINs", i assign the same IO std. to my design (HPSFPGA) as in sockit_ghrd design only to LED pins.

    it add the new error's related to new assignment saying that "Pin LEDR0 is incompatible with I/O bank 3A. it uses I/O standard 2.5 V, which has.....etc". similear to previous error's

    (2) How do i check .tcl script please put more light on it?.

    attached is the print-screen of both design's pin planner along with error being generated.

    Regards

    kaushal
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi,

    check the IO-Standard, it seems to be 2.5V in your Design, but has to be 3.3V LVTTL to work.

    Please check that for all the Banks within your Design, but what is the obstacle, that you do not put the small amount of changes within the GHRD and compile that?

    Later on you may evaluate what are the differences.

    Kind regards
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hello Taz,

    Thanking you for your response and time.

    Yes ! i have tried what you mentioned in your post, but every time i assign the I/O to Desired Pin like "HPS_ENET_GTX_CLK" to H19 from bank 7B , it says not assignable as this bank is not visible in drop down menu in pin assignment windows. whereas i have to assign this HPS_ENET_GTX_CLK to H19 only as per data sheet. and same thing happen for rest of the pins describe in error's.

    i have attached the Print-Screen for same what i have tried .

    Regards

    Kaushal
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Kaushal,

    the dedicated HPS-PINs are not asignable due to a hardwired connection, try to not assign them (like in the GHRD).
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hello Taz,

    OK after giving them 3.3 LVTTL I/O level all errors related to these pins has gone,

    And as you mentioned in your post these are dedicated pin's so need not to be assign (What i understand).

    Lastly after Fitter in assembler it says Can't save or open

    D://Q13.1 User/SoCKit/db/ip/hps_fpga/submodule/sequencer/alt_types.pre.h

    Thanx

    Regrads

    kaushal
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hello Taz,

    follow both the options but problem still remain same.

    1.> Remove db-Files (Then Regenerate the qsys and recompile the project)

    2.> add hps_fpga.qip to project file (lead to some more errors)

    Regards

    kaushal