Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFPGA memory initialization and management
Hi, my design is using a cyclone IV on-chip memory. I have two questions (for the moment): - when configuring the memory with qsys, I don't really understand the data-width choice. If it's 32-bi...
Altera_ForumHonored Contributor
Honored ContributorOK it IS an altsyncram.
The tstep signal is generated like that: process(clk, tckup)
begin
if rising_edge(clk) then
if (tckup='1') then
wen <= '1';
if tstep<25000 then
tstep <= tstep+1;
end if;
else
wen <= '0';
end if;
end if;
end process;
