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Altera_Forum's avatar
Altera_Forum
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11 years ago

FPGA memory initialization and management

Hi, my design is using a cyclone IV on-chip memory. I have two questions (for the moment): - when configuring the memory with qsys, I don't really understand the data-width choice. If it's 32-bi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

OK it IS an altsyncram.

The tstep signal is generated like that: 

	process(clk, tckup)
	begin
		if rising_edge(clk) then
			if (tckup='1') then
				wen <= '1';
				if tstep<25000 then
					tstep <= tstep+1;
				end if;
			else
				wen <= '0';
			end if;
		end if;
	end process;

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Better than what? You asked how you can initialize it from file.

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Better than a .hex file?