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Altera_Forum
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11 years ago

FPGA memory initialization and management

Hi, my design is using a cyclone IV on-chip memory. I have two questions (for the moment): - when configuring the memory with qsys, I don't really understand the data-width choice. If it's 32-bi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Read the code and see what it does with the altsyncram address port.

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Qsys tells it's an altera_avalon_onchip_memory2, I don't know if it's the same as altsyncram...

The address is controlled by a VHDL line:

	addr <= std_logic_vector(to_unsigned(tstep, addr'length));

Tell me if I shouldn't do that.

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File->New, Memory Files, Hexadecimal (Intel-Format) File.

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Thanks for that. Is the Memory Initialization File better?