Fmax for clksys (NIOSII in Cyclone Kit)

Any number of things could be wrong.

1) Does your hardware design meet timing?

2) Are your memory connections correct?

3) Is your input clock driving 125MHz?

4) If you are using SDRAM, are you putting the correct phase shift on the clock?

5) (I should have asked this first) What board are you using (Nios Development Board or a Nios Eval Kit)?