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Altera_Forum's avatar
Altera_Forum
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16 years ago

Flash read causes two reads

I have the Stratix III development kit with the 512-Mbit Intel part on it. My command writes appear to be correct, looking at it with SignalTap. I write to the base address a command such as ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

no that is not completly correct.

there is a difference between normal memory access and IORD_16DIRECT

as long as you use the IORD functions the byteenable indicated which bytes are needed.

monitor via signaltap these two cycles and have a look at the byteenable

i have such a module placed between avalon switch fabric and the external tristate bridge to get rid of these additional read cycles.

in normal memory access it doesn't matter if you read 1byte, 2 byte or 4 byte, the data master will always read 4 bytes (32bit access)