Flash read causes two reads

no that is not completly correct.

there is a difference between normal memory access and IORD_16DIRECT

as long as you use the IORD functions the byteenable indicated which bytes are needed.

monitor via signaltap these two cycles and have a look at the byteenable

i have such a module placed between avalon switch fabric and the external tristate bridge to get rid of these additional read cycles.

in normal memory access it doesn't matter if you read 1byte, 2 byte or 4 byte, the data master will always read 4 bytes (32bit access)