I have posted the FIFOed avalon UART in the Hardware Projects area. It is the standard UART that comes with Nios but it has additional features such as FIFOs and hardware CTS fifoed avalon uart project (http://www.niosforum.com/pages/project_details.php?p_id=89&t_id=18)

This implementation works really great! Everyone should use these! I have used them at up to 2 Mbps and I am now able to service the receive interrupt and read all incoming data. Thanks!

Hi Longshot, thanks for this new uart. I hope it will be part of the sopc ... One question comes into my mind. This module has hw cts. What about HW RTS support for RS485 half duplex transmission ? If you connect a MAX485 f.e. to implement a differential half duplex connection between nios2 and a multidrop differential bus, mostly the rts is used to switch between receive and transmit. if the uart would automatically switch from receive to transmit as long as there is data to be transmitted and then back to receive then the software would not need to monitor any buffer of fifo structure. This would make a RS485 connection fast in the point of switching between receive and transmit, the nios would not have to do that (inside the interrupt routine) The switchover from transmit to receive and vice versa is always a very important point to be monitored in multidrop half duplex application. if you transmit data and do not switch to receive mode fast enough you could miss the start of data if the system on the other side of the multidrop bus that ist trying to comunicate with you is very fast. i have seen this on new fast plc where they switch over from receive to transmit (to acknowledge the receive of your data) with less than a couple of bittime (1-2 bit time space after the your last stopbit before the send the first startbit). the fifo between nios and the uart even at 115200 bit/sec is not the problem. the main problem ist the switch time between tx and rx. anyway thanks for this uart. Michael Schmitt

I will look at adding that in my next version. It should not be hard to do. longshot --- Quote Start --- originally posted by mschmitt@Aug 28 2006, 04:12 AM hi longshot, thanks for this new uart. i hope it will be part of the sopc ... one question comes into my mind. this module has hw cts. what about hw rts support for rs485 half duplex transmission ? if you connect a max485 f.e. to implement a differential half duplex connection between nios2 and a multidrop differential bus, mostly the rts is used to switch between receive and transmit. if the uart would automatically switch from receive to transmit as long as there is data to be transmitted and then back to receive then the software would not need to monitor any buffer of fifo structure. this would make a rs485 connection fast in the point of switching between receive and transmit, the nios would not have to do that (inside the interrupt routine) the switchover from transmit to receive and vice versa is always a very important point to be monitored in multidrop half duplex application. if you transmit data and do not switch to receive mode fast enough you could miss the start of data if the system on the other side of the multidrop bus that ist trying to comunicate with you is very fast. i have seen this on new fast plc where they switch over from receive to transmit (to acknowledge the receive of your data) with less than a couple of bittime (1-2 bit time space after the your last stopbit before the send the first startbit). the fifo between nios and the uart even at 115200 bit/sec is not the problem. the main problem ist the switch time between tx and rx. anyway thanks for this uart. michael schmitt <div align='right'><{post_snapback}> (index.php?act=findpost&pid=17892) --- quote end --- --- Quote End ---

The FIFOed Uart calculates from a wrong clock if a sopc pll is used ... If you open the Configuration dialog and have a look at the Baud Rate you will see the value of the input clock. the value is wrong. it is the value of the input clock that enters the sopc and feeds the pll but not the one this module is connected to. as it is actually the c0 output of the pll. im my case 48MHz input and 64MHz output. all SOPC modules are connected to the 64MHz output of the pll. The dialog displayes the 48MHz what ist wrong in this case. But i am not shure if the values internaly calculated are based on 48MHz or 64MHz in my case ... regards. Michael

I&#39;m using the FIFOed avalon Uart with HW CTS RTS control flow to send data to a Bluetooth tranceiver at 921Kbps. The bluetooth tranceiver send the data to a PC through a virtual COM port configured at 921 kbps too. My problem is that from time to time one byte send by software seems to be sent twice by hardware !!! I send 1MByte through the Fifoed Uart in high speed so flow control is often used by the bluetooth tranceiver, according to bluetooth datarate.. It seems that when Fifo goes full or goes empty and then goes to in between state, the last or first byte is send twice. I can see that in the file received : it&#39;s almost perfect, but sometines there is a duplicated byte. I can see that all over the file in no coherant manner.. FIFO lenght : 1024 Circular buffer lenght : 4096 Does someone could try to explain what happens ?? Thanxxx

FIFOed Avalon Uart | Altera Community

58 Replies

Altera_Forum
Honored Contributor
14 years ago
Hi all,
I didn't exactly found which is the problem and moreover I don't know if it is only due to the high speed I'm using (460800 baud); what I deduced and supposed is that the problem is not the Avalon FIFOed UART (neither 16550 Opencore Uart) component but is how Nios handle interrupt in not edge level sensitive manner (clearly using Internal Interrupt Controller).
Anyway if somebody is interested I found some tricky to use within interrupt service routine that solved the problem. Feel free to contact me if somebody is interested. :)
Ciao,
Paolo
Altera_Forum
Honored Contributor
14 years ago
Does anyone have a version of Fifoed_Avalon_Uart that works with Quartus v8.1?
Yes I know this is a very old version of Quartus, but I need to rebuild a legacy project and have to use Quartus v8.1 in this instance.
Version 9.0 to 9.3 of the uart only works with Quartus v9.x and upwards.
Version 1.1 only works with Quartus 6.x and does not have tcl scripts.
Altera_Forum
Honored Contributor
14 years ago
Hi there,
i have tested the fifoed avalon uart and observed that the start bit and stop bits are longer than actual data bits by one clock period.
Any comments?
Altera_Forum
Honored Contributor
12 years ago
Hi,

I'm using the last version of fifoed Avalon UART under Q13.0SP1, and I see the following warning related to it:

Warning (10858): Verilog HDL warning: object is_parity_error used but never assignedwire is_parity_error

The warning is clear, I'd like to understand if this wire (is_parity_error) not drived by anyone, and used in one expression, is dangling undrived because it's superfluos, or for some reason should be correctly drived by some logic (that in this case is missing), and so it's a kind of bug that could arise when a parity error happens...

Any experience?
Can we safely ignore this warning?

Best regards
Gianluca
Altera_Forum
Honored Contributor
12 years ago
Hi Gianluca,
I'm sorry but I'm a firmware developer and therefore I have not so much experience about wiring. Anyway, projects which are currently using fifoed avalon uart are working correctly.
Ciao,
Paolo
Altera_Forum
Honored Contributor
12 years ago
my stupid question :
in this function : int fifoed_avalon_uart_write (fifoed_avalon_uart_state* sp, const char* ptr, int len, int flags)
What is values of Flags ?
Can anybody guide me an example ? (i'm using FIFOed Avalon Uart ver. 9.3)
Thank you.
Regards,
Hubert.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Hi all,
I didn't exactly found which is the problem and moreover I don't know if it is only due to the high speed I'm using (460800 baud); what I deduced and supposed is that the problem is not the Avalon FIFOed UART (neither 16550 Opencore Uart) component but is how Nios handle interrupt in not edge level sensitive manner (clearly using Internal Interrupt Controller).
Anyway if somebody is interested I found some tricky to use within interrupt service routine that solved the problem. Feel free to contact me if somebody is interested. :)
Ciao,
Paolo
--- Quote End ---

HI
I have the same problem and would need help to solve it.

Regard.
Altera_Forum
Honored Contributor
12 years ago
Hi

I'm having an issue with the FIFOed avalon uart. I get it to generate and compile. I have no problems with the altera uart except when I go to higher baud rates like 115.2K. So I'm attempting to use the FIFO-ed uart as a replacement but having no luck with it.

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FIFOed Avalon Uart

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