FIFOed Avalon Uart

I longshot.

I read thie part of forum and i'm really curious about your UART+FIFO block.

Can you send me that please?

My email: [email protected]

Well...i should send an array through UART RS232 but even if it seems ok the creation of the same array and creation file for UART...it seems doesn't send anything, or better, leds light switch on and off (and if i well remember it's a behaviour of a UART on function) but if i try to read bytes sended (By SerialVisa program) , nothing arrive and Visa time outs.

Have you some suggests?

Thank you

FIFOed Avalon Uart Project

..this file i'm referred to..Doesn't work

As a beginner to the world of Nios I'm wondering how this component (enhancement to the Altera UART) has been developed.

I read chapter 10 "Developing Components for SOPC Builder" found in the Quartus II Handbook which shows how to develop custom peripherals based on HDL files. When looking into the attached ZIP file, all I can find are some C and Perl files.

Was this component developed in VHDL and exported to Perl or were all of the enhancements directly added into the Perl script? Can anybody point me to literature that describes how I can enhance an arbitrary component originally created by Altera?

Thanks,

Markus

Has a new revision of FIFOed been released lately ? Any additional bug fixes ?

Also is there any way that I could add additional data as a seperate entry to the FIFO i.e. on receiving serial data for each byte\word written into the FIFO is there anyway that I could attach\write a Time Tag to be stored into the FIFO for each entry ?

If this is going to be too hard\impossible - then how can I use the standard SOPC UART with an external\internal FIFO that I can write TTAG values to for each serial massage stored in the FIFO ?

Thank you in advanced

Shmuel

Hello,

I'm having a problem in the compilation when the RX FIFO depth and TX FIFO depth are different.

It seems that there is a bug when generating the VHDL code:

If TX FIFO depth is 8 bytes and RX FIFO depth is 16 bytes:

Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 4 elements, but must have 3 elements

If TX FIFO depth is 8 bytes and RX FIFO depth is 32 bytes:

Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 5 elements, but must have 3 elements

And so on..

If the two depths are the same, no error occurs.

Is there anyone experiencing the same problem?

Thank you.

Looks like it is a problem in the hw.tcl file

I will post a new hw tcl file. give it a try.

Long shot

Dear Long shot,

Please could you let me know when you make the fix and if it works ?

Also is there any way for me to attach\insert additional external data to the Serial Data stored in the FIFO e.g. a Time Tag ?

How well does the FIFOed work - how well ahs it been tested ?

Thanks in advanced

Shmuel

I just tried to use the FIFOed UART for the first time and have had difficulties. I am using Quartus 8.1 so I used version 7.1 of the FIFOed UART. I have 3 instances of the UART in my design. When I compile the design I get the following errors:

system_description/alt_sys_init.c:83: error: `UART_RS232_FREQ' undeclared here (not in a function)

system_description/alt_sys_init.c:83: error: initializer element is not constant

system_description/alt_sys_init.c:83: error: (near initialization for `uart_rs232.freq')

system_description/alt_sys_init.c:84: error: `UART_EMM_FREQ' undeclared here (not in a function)

system_description/alt_sys_init.c:84: error: initializer element is not constant

system_description/alt_sys_init.c:84: error: (near initialization for `uart_emm.freq')

system_description/alt_sys_init.c:85: error: `UART_ISO_SCI_FREQ' undeclared here (not in a function)

system_description/alt_sys_init.c:85: error: initializer element is not constant

system_description/alt_sys_init.c:85: error: (near initialization for `uart_iso_sci.freq')

make[1]: *** [obj/alt_sys_init.o] Error 1

make: *** [system_project] Error 2

I have talked to my FAE who says that lots of customers have had success using this UART. He sent me his copy of the source files which all match the files from the forum.

In the system.h file it appears that there isn't a clock associated with the FIFOed UART which may be part of the problem. Is anyone else running into issues like this?

Hi,

great stuff.

One question, are you just wrapping the original avalon uart, or have you programmed it from the scratch?

We need to be able to change parity at run time, which is not possible with the standard avalon uart.

Would you consider including that if possible?

Apus