FIFOed Avalon Uart

Hello,

I'm having a problem in the compilation when the RX FIFO depth and TX FIFO depth are different.

It seems that there is a bug when generating the VHDL code:

If TX FIFO depth is 8 bytes and RX FIFO depth is 16 bytes:

Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 4 elements, but must have 3 elements

If TX FIFO depth is 8 bytes and RX FIFO depth is 32 bytes:

Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 5 elements, but must have 3 elements

And so on..

If the two depths are the same, no error occurs.

Is there anyone experiencing the same problem?

Thank you.