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Altera_Forum
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20 years ago

fifo interrupt

I've created and added a new component using sopc component editor. The component is some logic for an a/d chip and the megafunction fifo. I want to use the 'half full' flag as an interrupt. I can read data okay in a simple loop, but have not been able to generate an interrupt. I used the button_pio example as a guide (sans the mask and edge registers - I presume there are none), but never reach the breakpoint in the ISR. I used the HAL instruction

alt_irq_register(ADFIFO_0_IRQ, dummycontext, adfifo_isr);

The parameter values all look correct in debugger. I can run the button_pio interrupt code just fine and get an interrupt on button press. I verified the half full flag is toggling by bringing it out to a pin and it is connected to the IRQ signal in the SOPC builder.

Is there some other initialization I am missing?

Thanks for any and all advice,

Tim

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    I solved my own problem and thought I'd share what I came up with.

    I had a complicated vhdl section that was a sequence of vhdl code I converted to a .bdf symbol, added the FIFO symbol and converted back to vhdl. With this I could not get interrupts to occur even though it appeared correct (albeit convoluted).

    I rewrote my vhdl section to properly incorporate the FIFO (lpm_fifo_dc) as a component and connected in the port map

    wrusedw(7) => avs_irq --bit 7 is the half full flag in this case, 128 words

    rdempty => avs_dataavailable_n

    The component was then added to NIOS using SOPC builder.

    In the NIOS code, the irq is enabled as before. When half full, the interrupt service routine (adfifo_isr) gets called. It is important the isr disable itself immediatly since interrupts are level sensitive, not edge sensitive:

    alt_irq_disable (ADFIFO_0_IRQ);

    The isr then programs the dma to transfer the bytes (DMA_NBYTES=128 words * 4 bytes/word ) from the (half full) fifo:

    alt_dma_rxchan_prepare (dmarxchan, dma_wr_ptr, DMA_NBYTES, dma_done, NULL);

    The dma callback routine (dma_done) re-enables the irq

    alt_irq_enable (ADFIFO_0_IRQ);

    and the cycle repeats.

    Tim