fifo interrupt

I solved my own problem and thought I'd share what I came up with.

I had a complicated vhdl section that was a sequence of vhdl code I converted to a .bdf symbol, added the FIFO symbol and converted back to vhdl. With this I could not get interrupts to occur even though it appeared correct (albeit convoluted).

I rewrote my vhdl section to properly incorporate the FIFO (lpm_fifo_dc) as a component and connected in the port map

wrusedw(7) => avs_irq --bit 7 is the half full flag in this case, 128 words

rdempty => avs_dataavailable_n

The component was then added to NIOS using SOPC builder.

In the NIOS code, the irq is enabled as before. When half full, the interrupt service routine (adfifo_isr) gets called. It is important the isr disable itself immediatly since interrupts are level sensitive, not edge sensitive:

alt_irq_disable (ADFIFO_0_IRQ);

The isr then programs the dma to transfer the bytes (DMA_NBYTES=128 words * 4 bytes/word ) from the (half full) fifo:

alt_dma_rxchan_prepare (dmarxchan, dma_wr_ptr, DMA_NBYTES, dma_done, NULL);

The dma callback routine (dma_done) re-enables the irq

alt_irq_enable (ADFIFO_0_IRQ);

and the cycle repeats.

Tim