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Altera_Forum's avatar
Altera_Forum
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19 years ago

FIFO Interrupt

Hello to all,

i've mapped a FIFO into the address space of my NIOS processor. I simply created a non HDL based interface to readout data by just using the IORDDIRECT macro. The FIFO is written by additional on-chip logic. Now, i would like to have an interrupt to be generated , if the FIFO is half full, so i added an additional irq signal for that interface. My question is now how it is possible to reset/clear that interrupt in my c - isr.

Thanks,

Christian

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    hello christian 80

    normally you have an irq status register in your component.

    a bit in this register is set, when an irq happens, e.g. fifo half full,

    all bits in the status register are cleared, when the status

    register is read.

    the irq signal is set in the component, when the irq status register is != 0.

    e.g.

    irq <= &#39;1&#39; when irq_status(7 downto 0) /= b"0000_0000" else

    &#39;0&#39;

    your irq service routine in c starts normally with

    irq_service(...)

    {

    // read interrupt status register, clears all pending interrupts

    irq_status = IORD(base, IRQ_STATUS_REGISTER);

    ...

    ...

    }