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Altera_Forum
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16 years ago

Fft In Sopc

Guyz please help , if u have an idea. Uptil now i made a 64 point FFT using megacore and added it to the sopc as a new component but there are a lot of signals and so it gives me an error when ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Hi,

Thanks a lot for your advices. When implementing the FFT which method will be more efficient, in NIOS or hardware(logic gates)? The reason I ask is because from the method you mentioned it involve arrangement of data and multiplication of coefficient matrix, L. Understand that the FFT IP core from Altera consumed quite a lot of logic. Do you have any references to implement this from scratch? Thanks.

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I suppose that you could implement a full-custom FFT core. But, chances are that it will not be as effecient as the cores that Altera has already provided in the mega core. The method above can be implemented in software (utilizing the FFT megacore NIOS) without too much headache.

While I do not have a reference design for you, I can give you a rough step-by-step to implement it in software:

  1. Generate the largest FFT based upon the resources of your FPGA/development board.

  2. Next, you will need to create an SOPC system that contains a NIOS core, FFT wrapper (you can refer to the wrapper in a previous thread in this post), and also some memory. I recommend you use DDR if you have it available...but i suppose internal RAM could work. The wrapper is basically a shell that encapsulated the FFT component.

  3. Once your system is up and running, you can then write a program in C for NIOS that does all of the matrix operations for you. This is where this method loses efficiency - since NIOS is doing all of the math, it will be sllllooooooowww! The tradeoff however, is that you can accomplish larger FFTs that what is provided by Altera with relative ease.

There may be some other stuff in there that you need :) . It may be a good idea to place internal RAM in between NIOS and the FFT core (input side) as well as on the output side of the FFT. This will enable you to utilize the SGDMA for transfering data in and out of you FFT and also reduces the cycle count of the NIOS when running the program.

Implementing the FFT from scratch using logic is not trivial by any means. This method will be a lot easier.

Hope this helps!