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Altera_Forum
Honored Contributor
16 years agoFor the accelerator optimized FFT, I get the result as below: -
nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) FFT Benchmark Starting (this will take up to 20 seconds) - Running 1000 iterations for both software and hardware. - Each iteration runs a 256 point radix 2 FFT transformation. --Performance Counter Report-- Total Time: 2.18095 seconds (290792861 clock-cycles) +---------------+-----+-----------+---------------+-----------+ | Section | % | Time (sec)| Time (clocks)|Occurrences| +---------------+-----+-----------+---------------+-----------+ |Software Only | 98| 2.13722| 284962337| 1| +---------------+-----+-----------+---------------+-----------+ |HW Accelerated | 1.99| 0.04344| 5792204| 1| +---------------+-----+-----------+---------------+-----------+ The software only output data is correct The hardware accelerated output data is correct nios2-terminal: exiting due to ^D on remote you may clean the project and rebuild again. By the way, the definitions for the accelerator optimized FFT I build is as below: - #define BufferRAM1 (alt_16 *)0x0000 #define BufferRAM2 (alt_16 *)0x0200 #define BufferRAM3 (alt_16 *)0x0400 #define BufferRAM4 (alt_16 *)0x0600 #define CosRAM (alt_16 *)0x0800 #define SinRAM (alt_16 *)0x0A00 Regards, syleow