Forum Discussion
Altera_Forum
Honored Contributor
21 years agofor two cycles remember that:
Cycle 1 --> your hardware has to latch the data Cycle 2 --> your hardware has to process the data Cycle 3 --> the Nios has to read it back So when you think of two cycle you imagine steps 1 and 2, however you are creating the custom instruction for the Nios which has it's own latching to do. I was thrown off by this the first time I did a CC but after that I just got into a habit of figuring out the cycles for my hardware and adding one. In the Nios II ref. manual the latencies of the instructions are listed there. Being able to access memory across a bus in 2 cycles would result in a low fmax I'm sure.