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Altera_Forum
Honored Contributor
Honored ContributorExternal SRAM interface
From the Nios II DK, the two IDT SRAM's (256kB x 16) are set up in 32-bit words. Since our design will only use one SRAM of smaller size (128kB x 16), would I have to import, say a VHDL source, ...
Altera_ForumHonored Contributor
Honored Contributoryou should get the signals
nnnn_byteenablen[1..0] where nnnn is the name of your Avalon Tristate Bridge connect nnnn_byteenablen[0] to \BLE of SRAM connect nnnn_byteenablen[1] to \BHE of SRAM
