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Altera_Forum
Honored Contributor
Honored ContributorExternal SRAM interface
From the Nios II DK, the two IDT SRAM's (256kB x 16) are set up in 32-bit words. Since our design will only use one SRAM of smaller size (128kB x 16), would I have to import, say a VHDL source, ...
Altera_ForumHonored Contributor
Honored ContributorUse Interface to userlogic:
Bus Interface Type: Avalon Memory Slave select add generic list of ports and edit it to the following. PORT NAME | Width | Direction | Shared | Type address | 17 | input | yes | address write_n | 1 | input | yes | write_n read_n | 1 | input | yes | read_n writedata | 16 | inout | yes | data chipselect_n | 1 | input | --- | chipselect_n be_n | 2 | input | yes | byteenable_n timing: I use 2 wait and 1 hold cycle (can be optimized)
