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Altera_Forum
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16 years ago

External Slave reset/clk signals

Hi all, My typical method of interfacing my Nios/SOPC system with the rest of the logic on the FPGA is to create implement one or more avalon slaves outside of the SOPC module, and to add exter...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Someone asked me about this the other day as well. This sounds like a bug but if you create a component that contains a file that wires the clk/reset and slave ports to a conduit that should work around the issue you are seeing. So you would just need a conduit containing signals that are in the opposite direction as the internal ports and just wire them together.

The DDR SDRAM controller connects it's I/O through a conduit just like what I'm suggesting above (except the component contains more than just wires).