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Altera_Forum's avatar
Altera_Forum
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20 years ago

External Interrupts

I need to handle several external (to the FPGA) interrupts inside the NiosII core. I understand that I could use a PIO module and merely have an ISR respond to that interrupt and then route them myself. However, I am interested in modifying the uClinux code as little as possible and would prefer not to complicate the issue. So that being said I am wondering if I have another option besides making as many PIO modules as I have external interrupts to do this.

Merely as a reference I am using a NiosII/f with the PCI core from Altera and talking to several PCI devices including a OHCI1394 part.

Suggestions???

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Maybe you could create a SOPC Builder component with a single slave interface, which only has an IRQ pin on it? If you don't give it any HDL source files, it will just export the IRQ pin to the system module. Then you just have to create as many of these components as you need interrupts, and it's like having external IRQ pins.

    You'll need to rebuild the SOPC project and chip, but I don't think uClinux will need rebuilding (since there is no new address space taken and you don't have to initialize PIOs). Then you just have to hook in your interrupt handlers, and you should be good.