Forum Discussion
Altera_Forum
Honored Contributor
22 years agoExternal bus interface
I'm trying to implement something similar to the MMC interface with the Nios II through DMA and/or Avalon bus. This interface consists of 1 clock and 5 bi-directional data signals. In the ...
Altera_Forum
Honored Contributor
22 years agoOk, I've kept the address, write, read, and chipselect lines with the former 3 as shared. However, when I try to add bidirectional ports, the check mark in the shared box can't be unselected when define as data. The signals that I need to have come out externally don't get generated when either data or export is selcted as type. The way around this is to split each bidirectional port to have its own input and output ports, so it seems. It doesn't matter if the User Logic is set as Register or Memory slave.