Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
22 years ago

External bus interface

I'm trying to implement something similar to the MMC interface with the Nios II through DMA and/or Avalon bus. This interface consists of 1 clock and 5 bi-directional data signals. In the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
22 years ago

Thanks for the advice, and I'll try your suggestions.

I honestly don't know where e_signal came from, since I didn't assign it. I've unticked the import option on all the User Logic functions.

One last question, how is the Avalon register Slave different from the Avalon memory Slave? Aside from the typical naming and implication, I didn't quite find the answers in the PDF documents.