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SERMASWATHIKA's avatar
SERMASWATHIKA
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1 year ago

Error while generating bsp in nios tool

Hi Team,

We are working on migration project. Design is upgrading from 13.1 version to 22.1 version . In 13.1 version, exception vector of cpu is mapped to modified avalon and avalon is connected to DDR Memory. Now in 22.1 also, exception vector is modified same as 13.1 and error is showing for exception vector.

I have attached the error below:

Please check the error in the attachment. After modifiying the exception vector bsp is generated successfully.

Want to know the reason for the issue.

Nios Cpu

6 Replies

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Starting with the Nios® II EDS in the Intel® Quartus® Prime Pro Edition software version 19.2 and Intel® Quartus® Prime Standard Edition software version 19.1, the Cygwin component in the Windows* version of Nios II EDS has been removed and replaced with Windows Subsystem for Linux(WSL)


    Please refer below link on the WSL installation steps-

    https://www.terasic.com.tw/wiki/Getting_Start_Install_WSL


    Same type of issue is also posted earlier on forum-

    https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/failed-to-execute-wsl-dos2unix-create-this-bsp/m-p/1344838


    Regards

    Tiwari


    • SERMASWATHIKA's avatar
      SERMASWATHIKA
      Icon for Contributor rankContributor
      1 year ago

      Hi Jeet,

      Already ubuntu is installed in our pc and we compiled one board design without issue in eclipse tool. Now when we opened another board design in eclipse 22.1, again this error is popped out.

      When i changed the exception vector from modified avalon mem to ddr_avl , it is compiled.

      Thats why i am suspecting the exception vector of cpu .Can you please give clear guidance on this?

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Please confirm on below.

    The working design is with the quartus and eclipse v22.1?

    Also, The migrated design is upgraded from the v13.1 to v22.1 or you have created the design from the scratch in qaurtus v22.1 with the design reference v22.1?


    Regards

    Tiwari


    • SERMASWATHIKA's avatar
      SERMASWATHIKA
      Icon for Contributor rankContributor
      1 year ago

      Hi Jeet,

      Yes ,working design is with quartus and eclipse 22.1 .

      The migrated design is from 13.1 to 22.1 . Yes we have created the deisign from 13.1 version in Quartus 22.1 . In eclipse tool , for this design error is popping out.

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Can you share the snapshot of NIOS II IP settings which you have used in QSYS?


    Regards

    Tiwari


  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.