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Jayeshkumar's avatar
Jayeshkumar
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Error Code 8 Command: nios2-flash-programmer

We are facing an Error Code 8 Command: nios2-flash-programmer. can someone please help on this?
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Jayesh

For the error that you are facing could you send me a screen shoot of the whole error reported text and the nios2-flash-programmer command?

Furthermore could you also descript the environment you are working on? (eg. what board/ device you are using? )

At the meantime could you check the if there are any warnings/conflicts on the NIOS2 PLL settings for the SDRAM clock and the CPU clock?

It is recommended to have 3 separate clock source for the CPU, internal SDRAM module, and external SDRAM module.

Regards

Jingyang,Teh

  • Jayeshkumar's avatar
    Jayeshkumar
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello Jingyang,

    Following is the whole error:

    Info: 30 May, 2022 11:33:05 AM - (INFO) elf2flash: args = --input=C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/software/hello/hello.elf --output=C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/flash/hello_flash.flash --boot=C:/altera/15.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec --base=0xa000000 --end=0xc000000 --reset=0x0 --verbose
    Info: 30 May, 2022 11:33:05 AM - (FINE) elf2flash: Starting
    Info: 30 May, 2022 11:33:05 AM - (WARNING) elf2flash: Supplied reset address: 0x0 differs from the elf file reset vector: 0xa000000.
    Info: 30 May, 2022 11:33:05 AM - (FINE) elf2flash: Done
    Info: Using cable "USB-Blaster [USB-1]", device 1, instance 0x00
    Info: Resetting and pausing target processor: OK
    Info: No CFI table found at address 0x0A000000
    Info: Original contents (after writing 0xF0 and 0xFF00FF to address 0x0A000000):
    Info: 0: 98 00 00 01 3A 20 00 00 01 3A 88 01 00 01 37 42 ....: ...:....7B
    Info: 10: 80 08 01 3A 88 B3 C8 01 2C F0 81 C8 01 1E F8 3F ...:....,......?
    Info: 20: 10 01 35 D6 40 08 01 37 00 80 F0 01 35 BD 80 08 ..5.@..7....5...
    Info: 30: 01 C4 FF BF 00 01 35 F0 80 08 01 BA 30 05 00 01 ......5.....0...
    Info: 40: 7A 30 07 00 01 FA 30 09 00 01 3A 31 0B 00 01 35 z0....0...:1...5
    Info: Contents after writing 0x980098 to address 0x0A0000AA:
    Info: Same after writing 0x980098 to address 0x0A000154:
    Info: Same after writing 0x00980098 to address 0x0A0002A8:
    Info: Same after writing 0x980098 to address 0x0A000055:
    Info: Same after writing 0x980098 to address 0x0A0000AA:
    Info: Same after writing 0x00980098 to address 0x0A000154:
    Info: Same after writing 0x980098 to address 0x0A000154:
    Info: Same after writing 0x980098 to address 0x0A0002A8:
    Info: Same after writing 0x00980098 to address 0x0A000550:
    Info: 0: 98 00 00 01 3A 20 00 00 01 3A 88 01 00 01 37 42 ....: ...:....7B
    Info: 10: 80 08 01 3A 88 B3 C8 01 2C F0 81 C8 01 1E F8 3F ...:....,......?
    Info: 20: 10 01 35 D6 40 08 01 37 00 80 F0 01 35 BD 80 08 ..5.@..7....5...
    Info: 30: 01 C4 FF BF 00 01 35 F0 80 08 01 BA 30 05 00 01 ......5.....0...
    Info: 40: 7A 30 07 00 01 FA 30 09 00 01 3A 31 0B 00 01 35 z0....0...:1...5
    Info: Ignored possible autoselect code 04-04 as no override data
    Info: present in section [FLASH-04-04]
    Info: Ignored possible autoselect code 0004-0004 as no override data
    Info: present in section [FLASH-0004-0004]
    Info: Ignored possible autoselect code 00000004-00000004 as no override data
    Info: present in section [FLASH-00000004-00000004]
    Info: Leaving target processor paused
    Error: Error code: 8 for command: nios2-flash-programmer "C:/jayesh/AKASH_ARMY/mtx_firefly_4c40/flash/hello_flash.flash" --base=0xa000000 --accept-bad-sysid --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-1]' --program --verbose --erase-all

    We are using Device : Cyclone IV : EP4CE55F23I7

    The compile log report is attached herewith for your reference

    We are using external PLL IP where the source clk is 24MHz and it is constraint in sdc file. There are two output clocks both are 100MHz out of which one is used for external SDRAM (External to FPGA) and other is used for NIOS. There is no internal SDRAM used in our project.