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Benitez__Domingo's avatar
Benitez__Domingo
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Error: BSP component drivers cannot specify mutually independent interrupt APIs

Hi, I am trying to migrate a golden system reference design (GSRD) for the Terasic DE0-Nano board that is based on a Nios II/e processor to another GSRD for the same board but based on a Nios V/m pr...
Nios Cpu
AnnC_Altera's avatar
AnnC_Altera
Icon for New Contributor rankNew Contributor
1 year ago

Hi,

The component is “Parallel Port” under University Program and I wonder it is not in good status to support NiosV right now.

I would suggest you to replace them with the "PIO (Parallel I/O) Intel FPGA IP" and try it again to see if the error can be removed.

Best Regards,

Ann

Benitez__Domingo's avatar
Benitez__Domingo
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi,

The error was removed by replacing the “Parallel Port” under the University Program with the "PIO (Parallel I/O) Intel FPGA IP".


Thank you very much.


It would be nice if the "SDRAM controller IP" were available because the 32 MB of RAM memory available in the DE0-Nano board cannot be used. Anyway, some help to guide me in implementing such a memory controller is welcome.

Best regards,

Domingo