Occasional Contributor
New ContributorHi,
I understand the first interrupt line connected to the Nios V/m processor in your system is from "JTAT UART"?
For the second interrupt line, from which component in your system?
I wonder the issue is with the component you used in your system, but not the NiosV/m could not connect more interrupt line.
Best Regards,
Ann
Occasional ContributorHi,
Thank you very much for your question.
I think the issue is with the component.
When I connect both the JTAG UART and Interval_timer to the platform_irq_rx port of Nios V/m, there is no error during the generation of settings.bsp BSP file.
When the pushbuttons or one of the Expansion_JPx (x=1,2,3,3_in) controllers are connected to Nios V/m interrupt controller, the error is activated during the generation of settings.bsp BSP file.
Attached is the System Contents view of the Platform Designer tool for the GSRD on the DE0-Nano board when the error is produced in the case of only one interrupt line connected to the interrupt controller of Nios V/m.
Best regards
