EPCS IP Bootloader used to work
We have used a NIOS that boots from the epcs eeprom into a ddr bank before. It was on the Cygwin tools version of Quartus. We have actually done this a bunch of times.
The executable files have moved around, but I managed to use the same process with wsl that I was using with Cygwin.
/mnt/c/intelFPGA_lite/21.1/nios2eds/bin/sof2flash.exe --input=output_files/VXI_DA8.sof - output=hwimage.flash --epcs --verbose
/mnt/c/intelFPGA_lite/21.1/nios2eds/bin/elf2flash.exe --input=./mt_epcs.elf - output=swimage.flash --epcs --after=hwimage.flash --verbose
/mnt/c/intelFPGA_lite/21.1/nios2eds/bin/gnu/H-x86_64-mingw32/bin/nios2-elf-objcopy.exe -I srec -O ihex hwimage.flash hwimage.hex
/mnt/c/intelFPGA_lite/21.1/nios2eds/bin/gnu/H-x86_64-mingw32/bin/nios2-elf-objcopy.exe -I srec -O ihex swimage.flash swimage.hex
Then hwimage.hex and swimage.hex go into the jic.
I put a power up trigger into signal tap and watch it run, and it
never jumps into code.
It looks like the instruction pointer from the NIOS is waiting for
something to happen in the bootloader header in the epcs controller
IP. It says 0x24c, 0x250, 0x254, 0x24c, 0x250, 0x254, 0x24c, 0x250,
0x254, 0x24c, 0x250, 0x254, ...
Is there a known issue with this?
Does this work with the WSL version?
Thanks!!!