EPCS fpga+nios field update

Let me explain how this works. By the way yes you do have to write a custom bootloader.

1 - You power-up the board.

2 - The FPGA begins active serial configuration and programs itself using the FPGA image stored at address 0x0 of the EPCS flash.

3 - Once the FPGA is programmed, the NIOS processor starts up and boots from an onchip RAM block located inside the EPCS flash controller component in your SoPC builder system. This is the bootloader. The source code for this bootloader can be found in your altera install directory:

C:\altera\91\nios2eds\components\altera_nios2\boot_loader_sources

4 - The bootloader mentioned above looks at the FPGA image located at address 0x0 and determines how long the image is.

5 - The bootloader jumps to the end of the FPGA image where it expects to find the software image (ELF).

6 - The bootloader copies the software image to RAM and then executes a non-returnable jump to RAM to start your program running.

So what you need to do is create a modified bootloader that will intervene in this process after step 2. Your bootloader needs to:

1 - Determine which FPGA image just got loaded (application or factory).

2 - Decide what to do next. If the current running FPGA image is the factory image you can:

. a) stay in factory mode and load a factory software image.

. or

. b) use the remote update core to attempt to load the application image

3 - If the current running FPGA image is the application image then it stands to reason that you will want to load the application software.

It's unfortunate the the NIOS forum crashed some time ago as all this information has been detailed in the past.

Jake