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Altera_Forum's avatar
Altera_Forum
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21 years ago

EPCS Controller Woes....

Hello, Trying to port a NiosI project to NiosII. To get started I've successfully created my custom board, and made a minimal project with a NiosII/f and a NiosII/e and SDRAM. One ke...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hello All,

The snag turned out to be that my onchip exception memory was too small. I had it set to 512 bytes which was just a guess. NiosI requires only 256 bytes.

Anyway a search on Altera's Find Answers turns up info that doesn't specify this size.

As a temporary fix, I've set the Exception Address to sdram.

It would be nice to know how big this area needs to be and how it relates to ISR's. My system (and I imagine everyone elses?) needs to minimize IRQ latency. An app note or at least a FAQ probably wouldn't be out of the question. This very topic has been discussed at length on usenet. (related to register windows on NiosI)

Ken