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Altera_Forum
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21 years ago

EPCS Controller Woes....

Hello, Trying to port a NiosI project to NiosII. To get started I've successfully created my custom board, and made a minimal project with a NiosII/f and a NiosII/e and SDRAM. One ke...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hi Jesse,

Thanks for the extended response http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

My initial thought/fear was that the EPCS_controller had MRAM blocks specified or something, because I had selected Cyclone as my device. Anyway, it seems to be doing much better now.

I don&#39;t necessarily want to do anything a particular way. I&#39;m more asking what the best practice is for someone wanting to build a EPCS bootable, multiple cpu system. (easy debugging very important)

I wish the multi-cpu enhancements were here already! Doing this on NiosI means I&#39;ve got one cpu debugging off of JTAG and one off of the serial port. I&#39;d much rather have a unified/shared JTAG connection for the whole system. I may very well wind up needing a third cpu as well.

I notice in my dual NiosII system that the epcs_controller address space spans only 2047 bytes. (7FFH) Is this correct for a 4Mb EPCS? Or is that memory range something other than the bits in the device. I would expect to have at least 2Mbits or 250KB at my disposal.

My minimal dual N2 system now builds and so I&#39;m ready to dive into the IDE. Wish me luck.

Ken