EPCQ Bootloader problems

Quartus 15.0, Cyclone V design

I'm booting the FPGA from a Micron N25Q128 SPI flash and am trying to transition my NIOS to boot from SPI flash instead of onchip RAM. I've read all of the app notes, white papers, etc. that talk about booting from EPCQ flash and have followed the instructions to the best of my knowledge, but I'm seeing weird results.

My NIOS design currently includes a DDR3 controller (which seems to be working fine for the original design), a Serial Flash Controller (SFC), UART, sysid and timer. The NIOS points to SFC with offset 0x800000 for the reset vector and to DDR with offset 0x20 for the exception vector. I generate HDL in QSYS, no problems.

In Eclispe I build a BSP for the project and set all the linker sections to point to DDR, then generate the BSP. I clean build the application and Make Targets/Build/mem_init_generate.

I compile the Quartus project with no errors.

I convert programming files and build a JIC image that includes the SOF (offset 0x0) and the SFC.HEX images (offset 0x800000).

I launch the Quartus Programmer and load the JIC image into my flash device. I verify the flash just to make sure the image is correct.

When I reboot using the new image, the FPGA comes up but the NIOS does not appear to be functioning (I do not see the messages that I expect on the UART console port). When I reboot a second time I find that the image in flash has become corrupted and the FPGA will no longer boot.

If I download the SOF file directly to the FPGA through the JTAG port and launch a debug session in Eclipse (which writes the application code directly to DDR) everything works as expected. I've been chasing this for most of the week and have run out of ideas.

Any suggestions?

Michael