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Altera_Forum
Honored Contributor
Honored Contributorendless loop in stock interrupt handler
Hi people, a bit of information about my system first: - terasIC DE2-115 evaluation board with Cyclone IVE FPGA - Nios II/s CPU - also part of CPU block: SDRAM Controller, PIO, SysID, 2x ...
Altera_ForumHonored Contributor
Honored ContributorI am using altera software v12.0 sp1 and had an issue compiling the freeRTOS port for altera v12.0 first.
Had to enable ALT_LEGACY_INTERRUPT_API_PRESENT to make it compilable. As my problem seems to be interrupt related, I rethaught my step and ported the Nios2-port of FreeRTOS to the new ALT_ENHANCED_INTERRUPT_API_PRESENT by changing the way it registers its interrupts (just had to swap one line of code) But I still have exactly the same problem (endless loop in isr). Honestly I have no more ideas how to solve this, it's driving me crazy Any hints which could push me into the right direction?
